FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

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FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

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Authors

Marta Maschietto

Alessandro Leparulo

Stefano Vassanelli

Dataset

Dataset

FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

(MDPI AG, 2021) Mattia Tambaro; Marta Bisio; Marta Maschietto; Alessandro Leparulo; Stefano Vassanelli

URI

https://tustorage.ulb.tu-darmstadt.de/handle/tustorage/42118

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