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FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

Description

Toolbox-ID

jz000214-0010

Identifier(s)

https://tustorage.ulb.tu-darmstadt.de/handle/tustorage/42116

Publisher

MDPI AG

License

https://creativecommons.org/licenses/by/4.0/

Subject(s)

DDC(s)

610

Distribution(s)

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Distribution
FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings
Mattia Tambaro; Marta Bisio; Marta Maschietto; Alessandro Leparulo; Stefano Vassanelli
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Distribution
FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings
Mattia Tambaro; Marta Bisio; Marta Maschietto; Alessandro Leparulo; Stefano Vassanelli

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