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FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

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datacite.relatedItem.issue1
datacite.relatedItem.relatedIdentifierTypeISSN
datacite.relatedItem.relatedItemIdentifier2673-6470
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datacite.relatedItem.titleDigital
datacite.relatedItem.volume1
dc.contributor.authorMattia Tambaro
dc.contributor.authorMarta Bisio
dc.contributor.authorMarta Maschietto
dc.contributor.authorAlessandro Leparulo
dc.contributor.authorStefano Vassanelli
dc.date.accessioned2026-02-25T14:28:59Z
dc.date.available2026-02-25T14:28:59Z
dc.date.issued2021
dc.identifier.doihttps://doi.org/10.3390/digital1010003
dc.identifier.otherjz000214-0010
dc.identifier.urihttps://tustorage.ulb.tu-darmstadt.de/handle/tustorage/42116
dc.publisherMDPI AG
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subject.ddc610
dc.titleFPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings
dc.typeArticle
dcat.distribution.pdfhttps://tustorage.ulb.tu-darmstadt.de/handle/tustorage/42117
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