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FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

dc.contributor.authorMattia Tambaro
dc.contributor.authorMarta Bisio
dc.contributor.authorMarta Maschietto
dc.contributor.authorAlessandro Leparulo
dc.contributor.authorStefano Vassanelli
dc.date.accessioned2026-02-25T14:28:59Z
dc.date.available2026-02-25T14:28:59Z
dc.identifier.urihttps://tustorage.ulb.tu-darmstadt.de/handle/tustorage/42117
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subject.ddc610
dc.titleFPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings
dc.typepdf
dspace.entity.typeDistribution
relation.isDatasetOfDistributionc2b12ec0-08c8-45b1-be39-e9c3ccc8976d
relation.isDatasetOfDistribution.latestForDiscoveryc2b12ec0-08c8-45b1-be39-e9c3ccc8976d

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