A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology
| datacite.relatedItem.firstPage | 218 | |
| datacite.relatedItem.issue | 3 | |
| datacite.relatedItem.relatedIdentifierType | ISSN | |
| datacite.relatedItem.relatedItemIdentifier | 2674-0729 | |
| datacite.relatedItem.relationType | IsPublishedIn | |
| datacite.relatedItem.title | Chips | |
| datacite.relatedItem.volume | 1 | |
| dc.contributor.author | Junyao Li | |
| dc.contributor.author | Pak Kwong Chan | |
| dc.date.accessioned | 2024-03-28T11:00:16Z | |
| dc.date.available | 2024-03-28T11:00:16Z | |
| dc.date.issued | 2022 | |
| dc.identifier.doi | https://doi.org/10.3390/chips1030015 | |
| dc.identifier.other | jz000027-0007 | |
| dc.identifier.uri | https://tustorage.ulb.tu-darmstadt.de/handle/tustorage/1576 | |
| dc.publisher | MDPI AG | |
| dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | |
| dc.subject.ddc | 621.3 | |
| dc.title | A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology | |
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