Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

datacite.relatedItem.firstPage195
datacite.relatedItem.issue3
datacite.relatedItem.relatedIdentifierTypeISSN
datacite.relatedItem.relatedItemIdentifier2674-0729
datacite.relatedItem.relationTypeIsPublishedIn
datacite.relatedItem.titleChips
datacite.relatedItem.volume2
dc.contributor.authorSallar Ahmadi-Pour
dc.contributor.authorMathis Logemann
dc.contributor.authorVladimir Herdt
dc.contributor.authorRolf Drechsler
dc.date.accessioned2024-03-28T11:01:00Z
dc.date.available2024-03-28T11:01:00Z
dc.date.issued2023
dc.identifier.doihttps://doi.org/10.3390/chips2030012
dc.identifier.otherjz000028-0004
dc.identifier.urihttps://tustorage.ulb.tu-darmstadt.de/handle/tustorage/1620
dc.publisherMDPI AG
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.subject.ddc621.3
dc.titleSynergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
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